The subject method and system are generally directed to efficient yet accurate timing analysis for an electronic circuit design to verify compliance with the various timing constraints applicable thereto. More specifically, the subject method and system provide for optimization of timing windows for certain nodes of the electronic circuit design to facilitate the determination of certain signal integrity effects on timing, such as those due to crosstalk. The subject method and system thereby alleviate undue pessimism or optimism in the computation of such effects for certain timing paths defined through the electronic circuit design.
Various static timing analysis measures are known in the art. A static timing analysis (STA) is carried out to assess the timing of digital circuits using software techniques and certain models that provide relevant characteristics of the circuit in question. Electronic Design Automation (EDA) is widely employed for software design of such circuits, as part of the overall design and fabrication process. An EDA flow encompasses numerous stages, including a timing verification stage; and, STA is particularly useful when employed in the timing verification stage of an electronic circuit design, though it may be employed in connection with other EDA stages.
STA is carried out generally to compute the worst case and best case timing delays for all possible signal paths through the cells of a given circuit, without regard for logical operation. The circuit design is broken down into subsections traversed by various types of timing paths which collectively cover each and every combination of starting and ending points to determine the possible propagation delays therethrough. The timing information obtained is then compared to the timing constraints applicable to such paths. The timing constraints typically reflect such parametric factors as clock period, timing characteristics of certain inputs/outputs of the circuit, and the like.
The circuit design's compliance with applicable timing constraints may then be verified without having to precisely track each and every one of the possible signal paths. This enables relatively fast and computationally simple timing verification, especially for larger, more complex circuit designs. STA thus provides an efficient alternative to more computationally intensive measures for timing constraint verification like actual circuit simulation runs on the circuit design.
Different STA methodologies are known. They include graph based analysis (GBA), as well as the more exhaustive path based analysis (PBA). Such STA methodologies are carried out to analyze the timing of signal setup and signal hold delays, which are typically measured in terms of slack at certain nodes of the circuit, or the difference between required and arrival times of a signal at a node. Positive slack would indicate room for additional delay without detrimental effect on the overall circuit delay. Negative slack would indicate excessive delay in the timing path leading to that node requiring remedial measures to avoid detrimental effect on the speed of overall circuit operation.
In GBA, the various input models are read in, and a persistent model of STA is built. That is, the software executes to create internally a timing graph for the given netlist, then computes the worst arrival and required times at the various nodes of the graph. For certain nodes which may be characterized as endpoints, it also computes the worst slack.
The more exhaustive, computationally burdensome PBA methodology is an extension to GBA, and is typically used to target pessimism reduction that may have been introduced at various stages of GBA.
Yet the reliability of timing analysis is plagued by sources of undue pessimism and optimism. These sources vary. The types of pessimism introduced during GBA analysis, for instance, include:
1. Slew merging pessimism impacting delay computation on the timing network;
2. Graph based derating factors (advanced on-chip-variation factors); and,
3. Signal Integrity (SI) effects.
Various signal integrity (SI) analysis measures are also known in the art. SI analysis is carried out to verify the fidelity of signals passing from a certain driver component to a certain receiver component of a given electronic circuit design through a transmission line interconnect. SI analysis serves to characterize the quality of transmitted signals through physical interconnects employed in the circuit design like traces, connectors, vias, etc.
Efforts to address SI effects like crosstalk delay in the context of STA analysis have been made in the art. During the course of STA analysis, certain SI analysis measures, such as the so called path mode and overlap mode of crosstalk delay analysis, are employed to account for crosstalk effects in the given circuit design. But optimism is intrinsic to the path mode of such SI analysis; and, this optimism tends for example to cause undue optimism in GBA slacks. Conversely, pessimism is intrinsic to the overlap mode of such SI analysis; and, this pessimism tends for example to cause undue pessimism in GBA slacks. There is therefore need for a timing analysis approach which optimizes the SI analysis supporting GBA or other such timing analyses, by alleviating this undue pessimism and optimism in an efficient yet reliable manner.